In order to achieve reduction of the bit cost with the increase in capacity of a memory device, there are required miniaturization and improvement of the performance of each of the elements including a control circuit of the periphery of a memory cell array.
In the transistors constituting the control circuit, when the gate length is shortened to decrease the channel resistance, a parasitic resistance such as a resistance between the source-drain region and a contact electrode significantly affects the device characteristics, and therefore, the reduction of the parasitic resistance is required.